Peripheral Component Interconnect PCI

The Peripheral Component Interconnect (PCI) is a recent high-bandwidth, processor independent bus that can function as a mezzanine or peripheral bus compared with other common bus specification. PCI delivers better system performance for high-speed I/O subsystem. The current standard allows the use of up to 64 data lines at 33MHz for a raw transfer rate of 264 Mbytes/sec, or 2.112 Gbps. But it is not just a high speed that makes PCI attractive. PCI is specifically designed to economically meet the I/O requirements of modern system; it requires very few chips to implement and supports other buses attached to the PCI bus.

Intel began work on PCI in 1990 for its Pentium based system. Intel soon released all the patents to the public domain and promoted the creation of an industry association, the PCISIG, the further develop and maintain the compatibility of the PCI specifications. The result is that PCI has been widely adopted and is finding increasing use in personal computer, workstation and server system. The current version, PCI 2.0, was released in 1993. Because the specification is in the public domain and is supported by a broad cross section of the microprocessor and peripheral industry. PCI products built by different vendors are compatible.

A typical use of PCI in a single- processor system.

PCI is designed to support a variety of microprocessor-based configurations, including both single and multiple-processor systems. Accordingly, it provides a general-purpose set of function. It makes use of synchronous timing and a centralized aribitration scheme.

A combined DRAM controller and bridge to the PCI bus provides tight coupling with the processor and the ability to deliver data as high speeds. The bridge acts as a data buffer so that the speed of the PCI bus may differ from that of the processor’s I/O capability. In a multiprocessor system, one or more PCI configuration may be connected by bridges to the processors system bus.

The system bus supports only the processor/cache units, main memory and the PCI bridges. Again, the use of bridges keeps the PCI independent of the processor speed yet provides the ability to receive and deliver data rapidly.

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